IMS A1270 and A1320 Z80 CPU board - jumper and operation Developed by Roger Hanscom 2017 see https://sites.google.com/site/oldcpusrus/ims-z80-cpus edited by Herb Johnson Jan 2020, my edits in []'s Board top connectors J1-J6 Looking at the connectors on the top of the board, starting at the left, J1 is a "console switching" connector and J2 [only on the A1270] is used to switch port A to the console connector (J2 is only present on the master board). Since I'm not planning to use either of those console options, I ignored J1 and J2. J3 and J4 are 14-pin serial port connectors for port A and port B, respectively. These IMS boards have no serial line drivers on them, so the outputs at these connectors are TTL level. IMS used "paddle boards" that contained the classic 1488 and 1489 line drivers. I just did a 3-wire connection at J3/4 -- Tx, Rx, and ground [to a TTL/USB converter]. Curiously, there does not appear to be a good ground on either J3 or J4. I used the far left pin of J1, which is a direct connection to pin 50 (ground) of the S-100 bus. I had a lot of trouble getting any output from the boards until I inserted a null modem adapter at the DB-9 plug on the PC end. Their serial ports are apparently "full boat", and require all of the crossover that the null modem provides. Perhaps that can be modified (for those who want to do so) by fiddling with the Z8530 initialization code (more about that later). Here are the identities of a few of the pins on the J3 and J4 connectors that I traced (looking down at the top of the board): ------------------------- ------------------------- PCB^ | x x T x R C x | | x x S x x x x | T = Tx, R = Rx, C = CTS, S = RTS +---------------+ The J3 (Port A?) connector on the master CPU acts a little funny (probably because of the console options (J1 and J2)), but seems to work OK as a stand-alone console. Both connectors seem to have the same pin-outs, and I discovered that they are both serviced the same by the IMS monitor code. In other words, they are both (J3 and J4) sent the same characters, and are polled in the same way. J3 is addressed at 21h (status) and 23h (data), and I am calling it "Port A" (although that seems a bit arbitrary). J4 is addressed at 20h (status) and 22h (data). J5 is an interrupt daisy chain, i.e J5-2 gets connected to J5-1 on the first "user" CPU, and J5-2 on the first "user" CPU gets connected to J5-1 on the next, etc (in typical Zilog fashion). In the final analysis, no connection is made to J5-1 on the first board, or J5-2 on the last. Again, since I'm not interested in multi-user mode, I ignored J5. J6 is the parallel data cable used to transfer information to, and from, the system master to the "user" cards. Since I don't plan on using these CPUs in the multi-user configuration, I haven't made any attempt yet to figure out the pins on J6 (maybe later -- it might make a good "parallel port"!). I think (just a guess) that the address of J6 is 11h (and 12h?). I still haven't confirmed that at the moment. [J6 is likely driven by U6 and U7, both 74LS245's.] JA-JF OK, and then there are a bunch of connectors with the labels JA through JF. [These vary between the two boards.] JA [on the A1320 near J4]] is the last board shunt. Jumper 1-2 (top and middle) for last board. That's how my board is jumpered. JB [on the A1320, near J6] is the board address -- 0 for first (master) and increasing numbers for successive "user" boards. Looking at the connector from the front of the board, bit 0 is on the right, and bit 4 is on the left. The information I have says that it should *never* be jumpered all 1's (1Fh). Jumper up (toward the top of the board) for 1 and jumper down for 0. That being said, when running these boards in stand-alone mode, the configuration of this connector doesn't seem to matter at all. [On the A1320] JA and JB are combined into a single dip switch on the "user" board. The silk screen on my A1320 is self-explanatory as far as the settings for this switch are concerned. JC on the [A1320] "user" CPU is *very* important. It is on the top edge , and is three pins. Left and middle is "IPL" and middle and right is "test". It is nearer the center of the board on the master CPU. In that case, no jumper is "IPL", and jumper installed is "test". To run stand-alone, JC should always be "test". [JC on the A1270 is near U22 and open, function not established.] JD and JE are down near the voltage regulator on *only* the master [A1270] board. JD is for setting master/user options, and JE configures the board's interrupt configuration. If you are using the A1270 as a master, the jumpers on JD should be installed to the left (top is RDY, middle is XRDY, and bottom is "master"). If it is stand-alone, all jumpers should be right. JE enables S-100 interrupts (VI0 top, and then going down the connector, VI2, VI4, VI5, and finally VI7 at the bottom. If you are running as a master, all jumpers should be right (interrupts enabled). If you are running stand-alone, all jumpers should be left (disabled). JF [near U49 on either board] appears not to be used [?]. IPL monitor [From disassembly of the ROM monitor and an ICE, functions of the monitor were determined.] After locating the initialization strings for the Z8530, it was a simple matter to calculate that the console settings are 9,600 N81 when using the IMS firmware. If you want to make your board operate faster, locate the pair that sends a 10 (0Ah) to register 12 (0Ch), and change the 10 to 4 (19,200), 1 (38,400), or even 0 (57,600). As you can see in the disassembly, there are some parts that don't seem to get referenced/used, or I just don't understand. They have a ";???" comment after them. The sticky label on [my] A1270 EPROM is: IPL/MONITOR - REV 1.1 - D2CF U44; on the A1320 "user" EPROM is 1320 - REV 1.1 - D2CF U18. [The D2CF is a PROM programmer checksum.] "ims_mon.txt" is the partial dis-assembly of the IMS monitor on either. Port 10h plays a critical role in how the board starts up. Bit 0 of port 10h toggles between EPROM (0) and DRAM (1). Bit 1 is the DRAM bank select (bank 0 or 1). It seems that if bit 5 is a 1, the board will run the monitor at power up. And, I think if bit 7 is 1 the board starts to try to read something from port 12h, and executes accordingly (probably master/slave mode, with other "user" boards in the bus). Using the ICE on both boards, I found that outputing first a one to port 10h, and then a 20 to port 10h, I was able to start the monitor on both boards (by jumping to address 0h). I would guess that the port addresses at 20h (the serial ports) are not fully decoded, and thus repeat after 8. Same with the ports at 10h. Time-of-day clock After I stuck a fresh battery in the [A1270's] real time clock, I discovered that the ports at 60h-6Fh are the time of day and RAM locations for the MM58167 real time clock chip (on the master/slave board only). 60h thru 64h are the time, 65h is the day of the week, 66h is the date, and 67h is the month (described fully in the MM58167 documentation). 68h thru 6Fh are the chip's RAM locations (and they retain their contents after power down of the board). Other I/O ports There's also something at 70h. Don't know what yet. And maybe that address is not fully decoded, and repeats after 4? [A review of the disassembly gives a] list of ports used by the monitor as below. Some ports in the 8xh, 9xh, and Axh ranges don't look active in the output of my port read code, but they seem to be used in the monitor. IN: 10H, 11H, 12H IN: 20H, 21H, 22H, 23H IN: 88H, 90H, 97H IN: A0H, A1H, A6H, AEH OUT: 10H, 11H, 13H, 14H, 15H, 17H OUT: 21H, 22H, 23H OUT: 90H, 91H, 93H, 94H, 95H OUT: A0H, A1H, A7H, AFH Operation After using the ICE to start up both CPUs, I discovered that the master board (A1270) will start up on its own (without the ICE). But I haven't yet figured out how to get the "user" board (A1320) to start on its own. That board powers up with seemingly random junk in port 10h, so without the ICE to set port 10h properly, it will often just hang. I'm still working on that one. In a true multi-user configuration, it must get kick started somehow by the master? It probably will require custom firmware in a 27C64 EPROM? There is an LDIR loop at the beginning of the monitor code, but I think it is there just as a "stall" to let the hardware settle after a power up or reset. A little later in the firmware there is a small chunk of code that gets copied up to FC00H, and executed. It seems that this is what copies the monitor that is in EPROM to R/W memory at 0-1FFFh. I was able to extract part of the IMS EPROM monitor code that initializes the Z8530, and combine it with my own monitor, and I'm very happy to say that I was able to get it to work. - from notes by Roger Hanscom 2017 from Roger Hanscom Jan 2020 Both the boards that I was working with seem to be *very* nice. The good news is that the "user" board has a full set of S-100 fingers. Some other boards of that type, that I have seen, have only a few S-100 connections. The bad news is that it will take someone with more knowledge of electronics than I have to figure out how to get it to start up as a lone CPU. As I said in my [2017] analysis of the (A1320) board, it seems to start up with random bits in the port that controls its behavior. In order to get it to start stand-alone, someone will have to figure out how to force the content of that port. Too bad, because it is an 8 MHz board. The "master" board (A1270) seems to be a better candidate for stand-alone, but it is only 6 MHz. - Roger Hanscom Jan 2020