WPC 2BVZ WCourier 12 pt. 10 Pitchm[xxx,x  @P#;HP DeskJetHPDESKJE.PRSx  @x,,I@2Y9WA#xTI OmniLaser 2106/2115 (35 fonts)TO2135FO.PRSx  @:qCourierCourier BoldsgxxxX)Ex  @0sgxxxXFKx  `2 ,,  x Copies of this proposal may be purchased from: CAM/89-004 CAM Committee 408-867-6630 14426 Black Walnut Ct, Saratoga CA 95070 working document of the CAM (Common Access Method Committee) draft proposal EATA (Enhanced AT Bus Attachment) Rev 1.7a January 26, 1990 ABSTRACT: This standard defines the functional requirements for using SCSI commands with computers employing an AT Bus with intelligent peripheral devices. With the physical protocol of the AT Bus I/O, not all SCSI functionality is required. Consequently this standard includes a brief summary of SCSI functionality not included. The resulting interface provides a common interface specification for systems manufacturers, system integrators, controller manufacturers, and suppliers of intelligent disk drives. CAUTION: This is a preliminary draft of the proposed standard. It is subject to change without notice, at the sole discretion of the CAM Committee. It is likely that some sections may change significantly, and most sections will change to some extent in the course of further development of this draft standard. This draft is distributed solely for the purpose of review and comment, and it should not be used as a design document without assuming the risk of an early implementation. COPYRIGHT NOTICE: This draft standard is based upon product specifications of contributing members, these documents may be copyrighted by the individual companies. This draft standard may be reproduced without further permission, for the purpose of review and comment or for the purpose of including in an appropriate product specification provided the risk of early implementation is assumed. All other rights are reserved. POINTS OF CONTACT: I. Dal Allan (CAM Committee Chairman) ENDL 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6630  % If changes from the prior revision of this document are included, they may be identified by: - change bars at the side of each paragraph or - printed in bold or - printed in italics or - underscored in the text. The specific technique used will depend on the software used to detect the differences and the printer used to print the document. In the event that deleted text is identified by an overstrike, the Table of Contents will not be accurate. An electronic copy of this document is available from the CAM Committee (408-867-6630). This document has been prepared according to the style guide of the ISO (International Organization of Standards). If this document was printed in a 2-up form directly from the printer, NOTEs had to be adjusted to fit into a half-page, which may have resulted in an imperfect representation of the format within the NOTE. This is most likely to occur if a series of NOTEs are mixed in without any line separation.  P Common Access Method EATA Protocol Rev 1.7a January 26, 1990 TOC 1 TABLE OF CONTENTS 1. Scope 1 1.1 Description of Clauses 1 2. References 1 3. General Description 1 3.1 Structure 2 4. Definitions and Conventions 2 4.1 Definitions 2 4.2 Conventions 3 5. Interface Requirements 3 5.1 Configuration 3 5.2 Addressing Considerations 4 8. Overview 4 8.1 EATA Registers 5 8.1.1 Read/Write Registers 5 8.1.2 Status Register 5 8.2 Data Transfer Byte Orientation 6 9. EATA Commands 6 9.1 Read Config 6 9.2 Set Config 8 9.3 Send CP 9 9.4 Receive SP (Optional) 11 9.5 Truncate Transfer 13 9.6 EATA Command Protocol 13 10. EATA Master Mode DMA Overview 16 10.1 EATA Master Mode DMA Registers 16 10.1.1 Read/Write Registers 16 10.2 EATA Commands 16 10.3 Read DMA Config 17 10.4 Set DMA Config 18 10.5 Send DMA CP 19 10.6 EATA Master Mode DMA Command Protocol 21 11. Timing 22 11.1 Deskewing 22 11.2 Symbols 22 11.3 Terms 22 Annex A: Protocol Overview for a Driver 25  ' Common Access Method EATA Protocol Rev 1.7a January 26, 1990 TOC 2 FIGURES FIGURE 5-1: HOST BUS ADAPTER AND SCSI DEVICES 3 FIGURE 5-2: ATA INTERFACE TO CONTROLLER AND SCSI DEVICES 4 FIGURE 5-3: ATA INTERFACE TO EMBEDDED AT BUS PERIPHERALS 4 FIGURE 9-1: ORIGINATE COMMAND 14 FIGURE 9-2: RESPOND TO INTERRUPT 15 FIGURE 11-4: SEND CP PROTOCOL 23 FIGURE 11-5: RECEIVE SP PROTOCOL 24 TABLES TABLE 8-1: EATA REGISTER SETS 5 TABLE 9-1: EATA COMMANDS 6 TABLE 9-2: READ CONFIG (DATA IN) 7 TABLE 9-3: SET CONFIG (DATA OUT) 8 TABLE 9-4: SEND CP (DATA OUT) 10 TABLE 9-5: TARGET MESSAGE EXAMPLE 11 TABLE 9-6: RECEIVE SP (DATA IN) 12 TABLE 10-2: EATA COMMANDS 17 TABLE 10-3: READ DMA CONFIG 18 TABLE 10-4: SEND DMA CP 20  P Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 1 Information Processing Systems -- Common Access Method -- EATA Protocol 1. Scope This standard defines the EATA (Enhanced AT Bus Attachment) Protocol for AT bus applications. NOTE: PC AT is a registered trademark of IBM. EATA provides a structured method for supporting peripherals with the software (e.g. device driver) and hardware (e.g. host bus adapter) associated with an AT bus-based computer. The CAM Committee was formed in October, 1988 and the first working document of the EATA protocol was introduced in March, 1989. 1.1 Description of Clauses Clause 1 contains the Scope and Purpose. Clause 2 contains Referenced and Related International Standards. Clause 3 contains the General Description. Clause 4 contains the Glossary. Clause 5 contains the Description of the Environment of Use. Clause 8 contains the Enhanced AT Attachment structure. Clause 9 describes the commands used in SCSI pass-through mode. Clause 11 contains the interface timing diagrams. Annex A is informative. 2. References ISO DIS 10222 (dpANS X3.170-198x) ESDI, Enhanced Small Device Interface ISO DIS 10288 (dpANS X3.131-198x) SCSI-2, Enhanced Small Computer Sytems Interface CAM Committee Document CAM/89-002 ATA (AT Bus Attachment)  h) Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 2 3. General Description The application environment for the Enhanced AT Bus Attachment is any computer which uses a PC AT Bus or 40-pin ATA interface. The AT Bus is a widely used and implemented interface for which a variety of peripherals have been manufactured. As a means of reducing size and cost, a class of products have emerged. These new products utilize the PC AT fixed disk interface protocol, and a subset of the PC AT bus. Because of their compatibility with existing PC AT hardware and software this interface qickly became a de facto industry standard. The purpose of EATA provides enhancements to this interface which permit the attachment of a wide variety of peripherals which were built with SCSI (Small Computer Systems Interface). Software in the Operating System dispatches I/O (Input/Output) requests via the AT Bus to peripherals which are capable of recognizing commands which are "passed through" via the AT Bus to SCSI-based peripherals. 3.1 Structure The standard defines the methods by which commands are directed to peripherals, the contents of registers and the method of data transfers. 4. Definitions and Conventions 4.1 Definitions For the purpose of this standard the following definitions apply: 4.1.1 ATA (AT Bus Attachment): The interface derived from the original IBM PC AT rigid disk interface. ATA defines a compatible register and a 40-pin connector and its associated signals. 4.1.2 EATA (Enhanced AT Bus Attachment): This specification defines EATA, an interface which allows SCSI host adapter implementation with minimum modifications to existing ATA hardware. 4.1.3 CAM (Common Access Method): A specification defining several layers of standardization within operating systems software and peripheral controller hardware. EATA defines one possible implementation of the lowest layer of CAM. 4.1.4 CDB (Command Descriptor Block): A block of information containing the SCSI opcode, parameters, and control bits for that operation. 4.1.5 Nexus: A block of information containing the SCSI device, LUN, and Queue Tag Number (if any, as used in command queuing). 4.1.6 CP (Command Packet): A block of information containing the SCSI CDB and Nexus, along with other miscellaneous fields. The CP is issued to the EATA controller by the driver. 4.1.7 DMA (Direct Memory Access): A means of data transfer between peripheral and host memory without processor intervention.  . Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 3 4.1.8 PIO (Programmed Input/Output): A means of data transfer that requires the use of the host processor. 4.1.9 SP (Status Packet): A block of information containing the SCSI Nexus and Status, along with other miscellaneous fields. The SP is received by the driver from the EATA controller in response to a previously issued CP. 4.1.10 Optional: This term describes features which are not required by the standard. However, if any feature defined by the standard is implemented, it shall be done in the same way as defined by the standard. Describing a feature as optional in the text is done to assist the reader. If there is a conflict between text and tables on a feature described as optional, the table shall be accepted as being correct. 4.1.11 Reserved: Where this term is used for bits, bytes, fields and code values; the bits, bytes, fields and code values are set aside for future standardization. 4.1.12 VU (Vendor Unique): This term is used to describe bits, bytes, fields, code values and features which are not described in this standard, and may be used in a way that varies between vendors. 4.2 Conventions Certain terms used herein are the proper names of signals. These are printed in uppercase to avoid possible confusion with other uses of the same words; e.g., ATTENTION. Any lowercase uses of these words have the normal American- English meaning. A number of conditions, commands, sequence parameters, events, English text, states or similar terms are printed with the first letter of each word in uppercase and the rest lowercase; e.g., In, Out, Request Status. Any lowercase uses of these words have the normal American-English meaning. The American convention of numbering is used i.e., the thousands and higher multiples are separated by a comma and a period is used as the decimal point. This is equivalent to the ISO convention of a space and comma. American: 0.6 ISO: 0,6 1,000 1 000 1,323,462.9 1 323 462,9 5. Interface Requirements 5.1 Configuration This standard does not require a specific hardware configuration. A configuration may be based on an ATA peripheral which has the ability to process SCSI commands in a pass-through mode. Another configuration may be a host bus adapter which responds to the same commands as an ATA peripheral and has a SCSI port to attach internal or external SCSI peripherals.  P- Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 4 +-----------------------------------------------------+ | | | HOST | | | +------+====== AT Bus ======+-------------------------+ | | | CONTROLLER | | | +---^----^---^-------+ | | |__________________ | ___|_________________ | SCSI |/ | | | +-v----v--+ +-v----v--+ | DRIVE | | DRIVE | +---------+ +---------+ FIGURE 5-1: HOST BUS ADAPTER AND SCSI DEVICES +-----------------------------------------------------+ | | | HOST | | | +---------------^-------------------------------------+ | ATA Interface +------v-----+ | | | CONTROLLER | | | +-^----^---^-+ | | |__________________ | ___|_________________ | SCSI |/ | | | +-v----v--+ +-v----v--+ | DRIVE | | DRIVE | +---------+ +---------+ FIGURE 5-2: ATA INTERFACE TO CONTROLLER AND SCSI DEVICES +-----------------------------------------------------+ | | | HOST | | | +---------------^-------------------------------------+ | ATA Interface | _____________________ |/ | +------v--+ +------v--+ Embedded AT Bus | DRIVE | | DRIVE | Drives +---------+ +---------+ FIGURE 5-3: ATA INTERFACE TO EMBEDDED AT BUS PERIPHERALS 5.2 Addressing Considerations The SCSI nexus is indirectly addressed by using the ATA data transfer commands.  . Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 5 8. Overview The EATA provides for a SCSI host adapter to be designed by making a minimum number of modifications to an ATA implementation. EATA provides support for command queuing (therefore, command overlapping), potential reduction in operating system context switching and full CDB handling. Two information blocks shall be passed between the driver and the EATA controller: - the CP (Command Packet), issued by the software device driver, contains the SCSI CDB, and Nexus (SCSI device, LUN, and Queue Tag Number). - The SP (Status Packet) contains the Nexus, intermediate status, and the SCSI Status which is returned by the controller after an interrupt. This indicates which of the overlapped commands is in need of service, thereby re-establishing the logical thread. The CP and SP information blocks are passed through the 16-bit data register using the same PIO (Programmed Input Output) protocol as in ATA, which typically supports only 512 byte transfers. The transfer of a CP or SP begins as a normal 512 byte transfer, but at the end of the CP or SP block a Truncate Transfer command may be issued to the controller to abort the data transfer (thus reducing unnecessary transfers which constitute overhead). The Truncate Transfer command may only be issued when BSY is negated, and only during a data transfer. When Truncate Transfer is received, the controller hardware shall automatically abort the data transfer, and set DRQ=0 and BSY=1. 8.1 EATA Registers The EATA register set, as shown in Table 8-1, has been changed very little from ATA to allow backward compatibility. 8.1.1 Read/Write Registers - the 1F6 Drive/Head register is required to be loaded with the address of the ATA device which is to interpret the command. Non-ATA devices shall ignore this register. - the 1F7 Command register is loaded with the command opcode. - the 1F0 Data Register is a 16-bit read/write register used for PIO transfers of all data. Typically data transfers are always 512 bytes, unless they are aborted early due to receipt of a new command.  #  Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 6 TABLE 8-1: EATA REGISTER SETS +-----+-----+-----+-----+-----+-----+-----+-----+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +-------+----------+-----+-----+-----+-----+-----+-----+-----+-----+ | Write | Port 1F6 | 1 | 0 | 1 | DRV | HS3 | HS2 | HS1 | HS0 | | +----------+-----+-----+-----+-----+-----+-----+-----+-----+ | | Port 1F7 | COMMAND | | +----------+-----------------------------------------------+ | | Port 1F0 | DATA REGISTER (16 BITS) | +-------+----------+-----+-----+-----+-----+-----+-----+-----+-----+ | Read | Port 1F8 | 0 | 0 | 0 | 0 | 0 | 0 | IRQ | ABSY| | +----------+-----+-----+-----+-----+-----+-----+-----+-----+ | | Port 1F7 | BSY | RDY |FAULT| SC | DRQ | CORR| MORE|ERROR| | +----------+-----+-----+-----+-----+-----+-----+-----+-----+ | | Port 1F1 | BAD | ECC | 0 | RNF | 0 |ABORT| TR0 | DAM | | +----------+-----+-----+-----+-----+-----+-----+-----+-----+ | | Port 1F0 | DATA REGISTER (16 BITS) | +-------+----------+-----------------------------------------------+ NOTE: The EISA slot-specific addresses available on EISA machines correlate directly to AT Bus I/O registers: 1F0-1F8 = 0zC88-0zC90. 8.1.2 Status Register The 1F7 read register is referred to as the Status register. To enhance performance related to context switching, a new bit (MORE) has been defined. All other bits are unchanged. - MORE=1 after a data transfer indicates that the controller will have more data very soon, e.g., in a buffer or a cache, and requests that the driver poll BSY and DRQ for an indication of more data instead of performing a context switch. This can be done to avoid context switching between every block, but it is up to the controller to make a good definition of 'soon' relative to the time it takes an operating system to context switch. The controller should not set MORE during data reads from a disk which does not have a 1:1 interleave. 8.1.3 Auxiliary Status Register The 1F8 read register is referred to as the Auxiliary Status Register. Reading this register will not clear the interrupt. - ABSY=1 has the same meaning as BSY, but may be polled after without clearing the drive interrupt. - IRQ=1 shall be set when a drive interrupt is asserted and is typically used with level-triggered interrupts. 8.2 Data Transfer Byte Orientation The Intel CPU chip set swaps bytes and words on a memory access. The following is a representation to assist converting CP and SP bytes to a PC AT orientation.  *  Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 7 CP, SP etc 1F0 Data Register ---------- ----------------- bit 7-0 bit 15-8 bit 7-0 byte 00 byte 00 byte 01 01 02 03 02 04 05 03 04 05 The example assumes that the byte structure (CP, SP, etc.) is created one byte at a time, in the order 0, 1, 2, etc. As the PIO transfer is a word, the CPU swaps bytes when writing to the data register 1F0. This scheme is also valid during data register reads. 9. EATA Commands Five commands have been added to the ATA command set to facilitate transfer of Configuration Information, CDB's, and Nexus', and are passed through register 1F0. The other registers (1F6-1F1) are not used because all parameters and data are transferred through the data register. The commands fall into the categories of Data In, Data Out and No Data. TABLE 9-1: EATA COMMANDS +-----+-----+-----+-----+-----+-----+-----+-----+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +--------------+----------+-----+-----+-----+-----+-----+-----+-----+-----+ | Read Config | Data In | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | | Set Config | Data Out | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | | Send CP | Data Out | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | | Receive SP | Data In | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | | Truncate Xfr | No Data | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +--------------+----------+-----+-----+-----+-----+-----+-----+-----+-----+ 9.1 Read Config Read Config is issued during boot-up: - the operating system can determine the configuration of the controller - the operating system can determine if the controller supports EATA - the other four EATA commands are enabled To disable the EATA interface, the controller may be reset using the Init bit in the CP, or by setting the EDIS bit in the Set Config Data. This command cannot be overlapped the first time it is issued. For overlapped operation, the controller shall support the Receive SP command, which is not enabled until the first Read Config command has completed. The data descibed in Table 9-2 is returned by a Read Config command. A transfer of 512 bytes is required, even though all bytes are not needed for information purposes, because the Truncate Transfer command is not enabled.  +  Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 8 TABLE 9-2: READ CONFIG (DATA IN) ============================================================================== Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Byte | | | | | | | | | ============================================================================== 0 | (MSB) | - - -|- - READ CONFIG DATA LENGTH - -| 3 | (LSB) | -----|-----------------------------------------------------------------------| 4 | (MSB) | - - -|- - EATA SIGNATURE - -| 7 | (LSB) | -----|-----------------------------------------------------------------------| 8 | VERSION LEVEL | (00) | -----|-----------------------------------------------------------------------| 9 | HAAVAL | ATA | (00) | MORSUP | TRXFR | TARSUP | OCSENA | -----|-----------------------------------------------------------------------| 10 | (MSB) | - - -|- - CP PAD LENGTH - -| 11 | (LSB) | -----|-----------------------------------------------------------------------| 12 | (MSB) | - - -|- - HOST ADAPTER ADDRESS - -| 15 | (LSB) | -----|-----------------------------------------------------------------------| 16 | (MSB) | - - -|- - CP LENGTH - -| 19 | (LSB) | -----|-----------------------------------------------------------------------| 20 | (MSB) | - - -|- - SP LENGTH - -| 23 | (LSB) | -----|-----------------------------------------------------------------------| 24 | (MSB) | - - -|- - QUEUE SIZE - -| 25 | (LSB) | -----|-----------------------------------------------------------------------| 26 | | to | (00) | 511 | | ============================================================================== - READ CONFIG DATA LENGTH: The number of valid bytes following this field. - EATA SIGNATURE: an ASCII string of "EATA" (x'45415441') used to positively identify a controller supporting EATA. A driver can identify this code to insure detection of controllers not adhering to this specification, but which use this opcode for another purpose. - VERSION LEVEL: The version of the EATA standard to which the controller conforms. A version change indicates a published change in the standard.. - OCSENA=1 (Overlap Command Support Enabled): The controller supports overlapped commands and the overlapped feature has been enabled via the Set Config command. Overlap shall be allowed by the controller negating BSY when it is able to accept another command. An overlapped command shall require a Receive SP command after every interrupt. If OCSENA=0 the driver may choose to not issue the Receive SP and instead monitor the state of BSY. OCSENA should be clear by default. - TARSUP=1 (Target Mode Supported): The controller supports SCSI Target Mode. .  Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 9 - TRNXFR=1 (Truncate Transfer Cmd NOT Necessary): The controller supports a transfer of CP and SP without the Truncate Transfer command being issued. Normally, a controller would only be able to transfer in bursts of 512 bytes. If this bit is set, then an exact transfer of CP or SP length will occur. Reception of the Truncate Transfer command will not be considered as an error condition. - MORSUP=1 (More Supported): The controller supports the MORE bit in the Status register. If MORSUP=0, the MORE bit reverts back to its usual meaning, INDEX. - HAAVAL=1 (Host Adapter Address Valid): The Host Adapter Address is valid. - ATA=1: indicates that this is an ATA device and the Head/Drive register is required on every command. - CP PAD LENGTH: The number of pad bytes sent to the controller during a Send CP command following the valid CP data. Pad bytes provide tolerance before the Truncate Transfer command is accepted for EATA controllers which might otherwise not have sufficient time to store the CP because of a large buffer latency. Controllers which prefer a full data transfer without using a Truncate Transfer command set Pad Length to (512 bytes less CP Length). - HOST ADAPTER ID: The current SCSI Device ID for this controller if it is a SCSI Bus Host Adapter. All other controllers shall set this field to zero. - CP LENGTH: The number of valid CP information bytes sent to the controller during a Send CP command. - SP LENGTH: indicates the number of bytes returned to the driver during a Receive SP command. - QUEUE SIZE: indicates the maximum number of CPs which can be queued. 9.2 Set Config Set Config is issued to modify the default configuration of the controller. This command may be issued at any time the EATA interface is enabled. The data in Table 9-3 is transferred during a Set Config command. Although all 512 bytes are not defined, all 512 bytes shall be transferred. TABLE 9-3: SET CONFIG (DATA OUT) ============================================================================== Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Byte | | | | | | | | | ============================================================================== 0 | | - - -|- - TRANSFER LENGTH - -| 1 | | -----|-----------------------------------------------------------------------| 2 | (00) | TARENA | MDPENA | OCENA | EDIS | -----|-----------------------------------------------------------------------| 3 | (00) | -----|-----------------------------------------------------------------------| 4 | | to | (00) | 511 | | ============================================================================== - TRANSFER LENGTH indicates the number of bytes following this field. - EDIS=1 indicates that the EATA interface should be disabled when the Set Config command completes. The default interface after a power-up shall be used, typically ATA. - OCENA=1 indicates that the controller may allow overlapped commands by negating BSY during an active command. If this bit is cleared, then the  .  Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 10 driver may poll BSY for command completion and may choose to not issue the Receive SP after each interrupt. This protocol is described in more detail later in the specification. - MDPENA=1 indicates that the controller shall transfer all Save, Restore, and Modify Data Pointer messages to the host, rather than rejecting the messages. For performance purposes, these messages should only be passed to the host if the Data Pointer actually changes. - TARENA=1 indicates that the controller shall function as a Target, and transfer CDB's to the host. This function will be further described in later revisions of this document. 9.3 Send CP Send CP is used to pass a SCSI CDB, Nexus, or a Vendor Unique command to the controller. The information is passed with a Data Out protocol which shall be truncated to the number of bytes specified by CP Length + Pad Length, as defined in Read Config Data. CP's may be issued to SCSI devices or controller devices, or both e.g. it is possible within this specification to implement an ESDI interface on a SCSI host adapter. To access the ESDI drives, send CP's with an address equal to the HBA Address reported in Read Config. The ESDI drives shall appear to the driver as drives controlled by a SCSI bridge controller, and the actual attachment to the HBA shall be transparent. Table 9-4 describes the data passed in the CP:  p Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 11 TABLE 9-4: SEND CP (DATA OUT) ============================================================================== Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Byte | | | | | | | | | ============================================================================== 0 | DIN | DOUT | INT | (00) | INIT | SRESET | -----|-----------------------------------------------------------------------| 1 | (00) | -----|-----------------------------------------------------------------------| 2 | (00) | -----|-----------------------------------------------------------------------| 3 | (00) | -----|-----------------------------------------------------------------------| 4 | (MSB) | - - -|- - DEVICE ADDRESS - -| 7 | (LSB) | -----|-----------------------------------------------------------------------| 8 | (MSB) | - - -|- - MESSAGE 0-3 - -| 11 | (LSB) | -----|-----------------------------------------------------------------------| 12 | (MSB) | - - -|- - CDB 0-11 - -| 23 | (LSB) | -----|-----------------------------------------------------------------------| 24 | (MSB) | - - -|- - DATA TRANSFER LENGTH - -| 27 | (LSB) | -----|-----------------------------------------------------------------------| 28 | (MSB) | - - -|- - VIRTUAL ADDRESS OF CP - -| 31 | (LSB) | ============================================================================== - DIN=1 indicates that the direction of transfer is In (from the Target to the host). - DOUT=1 indicates that the direction of transfer is Out (from the host to the Target). - INT=1 indicates that the controller should interpret the command packet directly and not pass it through to the SCSI target i.e. it is used to make direct requests of the controller such as obtaining inquiry information. - INIT=1 indicates that the controller should re-initialize and perform any necessary power-up self-tests before returning status. No CDB or messages are transferred when this bit is set. - SRESET=1 indicates that the SCSI Bus Reset signal should be asserted. No CDB or messages are transferred when this bit is set. - DEVICE ADDRESS: The SCSI Device ID of the Target which shall receive the CDB or message. - MESSAGE 0-3: The message bytes to be transferred to the Target. A byte containing 0 shall be considered a NOP message and shall not be transferred to the Target. These bytes are typically used to transfer the Identify, Queue, and Tag messages, thereby indicating the correct Nexus. Message bytes shall be transferred in the order 0-3. - CDB 0-11: The CDB field is transferred to the Target, unless one of the other bits e.g. SRESET=1, causes the field to be ignored. - DATA TRANSFER LENGTH: The maximum number of bytes transferred by the Target to or from the host memory. . Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 12 - VIRTUAL ADDRESS OF CP: The virtual address of the CP to be returned in the SP to assist the device driver to locate the CP which caused an interrupt. Table 9-5 represents an example of how the Message 0-3 field is used (Byte 8 is the bit representation of the Identify message). TABLE 9-5: TARGET MESSAGE EXAMPLE ============================================================================== 8 | 1 | DISPRI | LUNTAR | 0 | 0 | LUN | -----|-----------------------------------------------------------------------| 9 | QUEUE MESSAGE | -----|-----------------------------------------------------------------------| 10 | QUEUE TAG NUMBER | -----|-----------------------------------------------------------------------| 11 | (00) | ============================================================================== - DISPRI=1 indicates that the Disconnect Privilege should be granted to the SCSI Target. - LUNTAR=1 indicates that the CP is for a Target Routine, not a Target LUN. - LUN: The Target LUN or Routine which shall receive the CDB or message. - QUEUE MESSAGE: The type of Command Queuing message, if any, that should accompany the CDB, as indicated in the following chart: QUEUE MESSAGE DESCRIPTION ------------- ----------------------- 00H No message - no queuing 20H Simple Queue Tag 21H Head of Queue Tag 22H Ordered Queue Tag - QUEUE TAG NUMBER: The number which should be used if queuing is desired. 9.4 Receive SP (Optional) Receive SP is used to return information concerning a previously issued CP, thereby re-establishing a logical thread. The information returned consists of a Nexus, intermediate status, and SCSI Status. When the driver receives an interrupt a Receive SP command may be issued. The driver may then determine which CP is being serviced and check for a possible data transfer. If EOC=1, the command is complete. This command is optional and may not be issued by the driver if commands are not overlapped. The data in Table 9-6 is transferred to the driver by Receive SP.  % Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 13 TABLE 9-6: RECEIVE SP (DATA IN) ============================================================================== Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Byte | | | | | | | | | ============================================================================== 0 | EOC | CONTROLLER STATUS | -----|-----------------------------------------------------------------------| 1 | SCSI STATUS | -----|-----------------------------------------------------------------------| 2 | (00) | -----|-----------------------------------------------------------------------| 3 | (00) | -----|-----------------------------------------------------------------------| 4 | (MSB) | - - -|- - INVALID RESIDUE LENGTH - -| 7 | (LSB) | -----|-----------------------------------------------------------------------| 8 | (MSB) | - - -|- - VIRTUAL ADDRESS OF CP - -| 11 | (LSB) | -----|-----------------------------------------------------------------------| 12 | (MSB) | - - -|- - MESSAGE 0-11 - -| 23 | (LSB) | ============================================================================== - EOC (End of Command)=1 indicates that the command has completed. If commands are not overlapped, the BSY bit in the Status register may be used to detect the end of command condition. - CONTROLLER STATUS: The controller status or state related to the current command. Controller Status is always valid, regardless of the state of EOC. The following are valid controller status bytes: BYTE DESCRIPTION ---- -------------------------- 00h No Error 01h Selection Timeout 02h Command Timeout 03h SCSI Bus Reset Received 04h Initial Controller Power-up 05h Unexpected Bus Phase 06h Unexpected Bus Free 07h Bus Parity Error - SCSI STATUS: The SCSI Status received after the data transfer. This byte is zero if EOC=0. - INVALID RESIDUE LENGTH: The number of bytes not transferred during the current command. This field shall contain zero if all bytes specified by the transfer length in the command were transferred. - MESSAGE0-11: These messages indicate the Nexus responding to a previous CP (see Send CP), and a possible Save/Restore/Modify Data Pointer message if the MDPENA bit is set. These messages should be handled by the controller if a Data Pointer does not acutally become modified.  , Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 14 9.5 Truncate Transfer The CP and SP information blocks are passed through the 16-bit data register using the same PIO protocol as in ATA, which typically supports only 512 byte transfers. CP and SP blocks may be less than 512 bytes. The transfer of a CP or SP begins as a normal 512 byte transfer, but at the end of the CP or SP block a Truncate Transfer command can be issued to the controller. NOTE: A 512 byte block transfer on a typical 8MHz bus corresponds to a 2.8 MBs transfer rate. The block will typically be transferred in 183 usec, a large overhead for one CP and multiple SP's. By truncating the transfer, the information may be transferred in 11 usec and 9 usec for a CP and SP, respectively. The Truncate Transfer command has no data phase or any values in registers 1F6-1F1, but consists of only an opcode. This command falls into the category of No Data. Controllers which do not require the Truncate Transfer command may set the TRNXFR bit. The host may transfer the exact length of the CP or SP, with the controller automatically asserting BSY after the last byte. NOTE: The controller should support the Truncate Transfer regardless of the state of the TRNXFR bit. 9.6 EATA Command Protocol Variations in the protocol for handling CP, SP, and data allow optional support of overlapped commands and the status packet. Three basic protocol sequences shall be supported by an EATA controller: - Send CP - Receive SP - Service Interrupts The Service Interrupt Sequence contains several Receive SP sequences. All three sequences are combined to create a complete command. Figure 9-1 and Figure 9-1 are flow charts which indicate the basic flow of a CP, SP, and data. See Figure 11-4 and Figure 11-5 for a timing diagram of Send CP and Receive SP. The protocol for transferring data is based on the MORE and DRQ bits, and optionally with the Receive SP command and EOC bit. - The MORE bit is used to indicate that another block of data is being prepared for transfer. - After a data transfer of 512 bytes, the driver should check if MORE=1 and poll for DRQ=1. - If at any time MORE is cleared, discontinue polling DRQ and check for an error. - If no error exists and more data remains to be transferred, or EOC=0 in the SP, then the driver should wait for another interrupt from the controller. Two conditions can indicates the completion of a command:  . Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 15 - EOC=1 in the SP or - If commands are not overlapped, BSY=0 in the Status register after an interrupt. _______________ < BEGIN COMMAND > *1 | | +---------v---------+ +--------------------+ | Other Commands | YES | Overlapped Cmds | | Active? |----------->| Enabled? | +-------------------+ +--------------------+ | NO OCSENA=1 | | OCSENA=0 | | | |<--------------------------+ | | +-----v-----+ | | Queue Cmd | | | in OS | +---v----+ +-----------+ | Read | | +---------->| Status | | | +--------+ | | BSY=1 | | BSY=0 | +-------------+ | | | | +---v----+ ______v_______ | Send | <END OF COMMAND> *2 | CP | +--------+ | | ____v____ < WAIT > *3 NOTES: *1 - Driver begins processing of command from Operating System. *2 - Exit ADD routine and re-enter when current command completes. *3 - Wait for interrupt, poll for BSY if no overlapped commands, or context switch back to OS. FIGURE 9-1: ORIGINATE COMMAND  `" Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 16 | *6 +--------v--------+ *5 +---------+ EOC=1 | Overlapped Cmds |------>| Receive |-----+ +-----------------+ =1 | SP | | | OCSENA=0 +---------+ | | | EOC=0 | | +--------------+ | | | | +-v-----------v-+ | +---------------------->| Read | MORE=0, DRQ=0 | | +------------------->| Status |--------------------+ | | | +---------------+ | | | | MORE=1 | | MORE=x | | | | DRQ=0 | | DRQ=1 | | | +----------------------+ | | | | +-----------+ | | | +-------| Transfer |<----------------+ | | | 512 bytes | | | +-----------+ +-----------------------+ | | | +---------v---------+ | | Overlapped Cmds | | +-------------------+ | NO | | YES | +--------v-+ +-v-------+ | | Read | | Receive | | | Status | | SP | | +----------+ +---------+ | BSY=0 | | BSY=1 EOC=0 | | EOC=1 | | | | | | +-------+ | | +-----+ | | __v_________________v__ | | | < WAIT > *8 |<-----+ | | +------------------------------------------+ | ______v_______ <END OF COMMAND> *9 NOTES: *4 - An interrupt has been detected from the controller. *5 - Driver may choose, if only one command is outstanding, not to receive the SP and instead to take data. If DISPRI=1 in the Identify msg, the Target may return a Data Pointer msg and the SP shall be received. *6 - A command with no data transfer shall have EOC=1 at the first interrupt. *7 - Driver may choose, if only one command is outstanding, not to receive the SP and to instead use the ATA Status and Error registers for command status. *8 - Wait for another interrupt with more data available, avoiding a context switch. *9 - The command is complete. FIGURE 9-2: RESPOND TO INTERRUPT  , Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 17 10. EATA Master Mode DMA Overview The EATA interface described in Section 8 and Section 9 uses PIO (Programmed I/O) as its method of data transfer. A higher performance method using Master Mode DMA can provide a higher data transfer rate, as well as added features including Auto-Request-Sense, Scatter-Gather, and reduced processor overhead (by requiring only one interrupt per command). Two information blocks are passed between the driver and the EATA controller: - the CP (Command Packet), issued by the software device driver, contains the SCSI CDB, Nexus (SCSI device, LUN, and Queue Tag Number), DMA location, and Request Sense Data location. The location of this packet is given to the controller. - The SP (Status Packet) contains the Nexus, intermediate status, and the SCSI Status which is returned by the controller after an interrupt. This indicates which of the overlapped commands has completed. It is DMA'ed to the location specified by the CP. 10.1 EATA Master Mode DMA Registers The EATA register set shown in Table 10-1 is similar to PIO EATA to allow backward compatibility. 10.1.1 Read/Write Registers - the Command register is loaded with the command opcode. - the CP Address Resister is load with the location of the CP to be processed by the controller. TABLE 10-1: EATA REGISTER SETS +-----+-----+-----+-----+-----+-----+-----+-----+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +-------+----------+-----+-----+-----+-----+-----+-----+-----+-----+ | Write | Port 1F7 | COMMAND | | +----------+-----------------------------------------------+ | | Port 1F5 | CP ADDRESS (MSB) | | +----------+-----------------------------------------------+ | | Port 1F4 | CP ADDRESS | | +----------+-----------------------------------------------+ | | Port 1F3 | CP ADDRESS | | +----------+-----------------------------------------------+ | | Port 1F2 | CP ADDRESS (LSB) | +-------+----------+-----+-----+-----+-----+-----+-----+-----+-----+ | Read | Port 1F7 | BSY | RDY |FAULT| SC | DRQ | CORR| MORE|ERROR| | +----------+-----+-----+-----+-----+-----+-----+-----+-----+ | | Port 1F1 | BAD | ECC | 0 | RNF | 0 |ABORT| TR0 | DAM | | +----------+-----+-----+-----+-----+-----+-----+-----+-----+ | | Port 1F0 | DATA REGISTER (16 BITS) | +-------+----------+-----------------------------------------------+ 10.2 EATA Commands The five PIO EATA commands are reduced to three with DMA. An equivalent to Receive SP is not needed because SP's are automatically DMA'ed. An equivalent to Truncate Xfr is not needed as all transfers are DMA, not PIO.  . Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 18 TABLE 10-2: EATA COMMANDS +-----+-----+-----+-----+-----+-----+-----+-----+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +-----------------+-----+-----+-----+-----+-----+-----+-----+-----+ | Read DMA Config | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | | Set DMA Config | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | | Send DMA CP | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | +-----------------+-----+-----+-----+-----+-----+-----+-----+-----+ 10.3 Read DMA Config Read DMA Config is issued during boot-up: - the operating system can determine the configuration of the controller - the operating system can determine if the controller supports EATA To disable the EATA interface, the controller may be reset using the Init bit in the CP, or by setting the EDIS bit in the Set DMA Config Data. The controller will revert to the ATA PIO interface. The data descibed in Table 10-3 is returned by a Read DMA Config command.  P Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 19 TABLE 10-3: READ DMA CONFIG ============================================================================== Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Byte | | | | | | | | | ============================================================================== 0 | (MSB) | - - -|- - READ DMA CONFIG DATA LENGTH - -| 3 | (LSB) | -----|-----------------------------------------------------------------------| 4 | (MSB) | - - -|- - EATA SIGNATURE - -| 7 | (LSB) | -----|-----------------------------------------------------------------------| 8 | VERSION LEVEL | (00) | -----|-----------------------------------------------------------------------| 9 | HAAVAL | ATA | (00) | DMASUP | (00) | TARSUP | OCSENA | -----|-----------------------------------------------------------------------| 10 | (MSB) | - - -|- - CP PAD LENGTH - -| 11 | (LSB) | -----|-----------------------------------------------------------------------| 12 | (MSB) | - - -|- - HOST ADAPTER ADDRESS - -| 15 | (LSB) | -----|-----------------------------------------------------------------------| 16 | (MSB) | - - -|- - CP LENGTH - -| 19 | (LSB) | -----|-----------------------------------------------------------------------| 20 | (MSB) | - - -|- - SP LENGTH - -| 23 | (LSB) | -----|-----------------------------------------------------------------------| 24 | (MSB) | - - -|- - QUEUE SIZE - -| 25 | (LSB) | -----|-----------------------------------------------------------------------| 26 | (MSB) | - - -|- - SG SIZE - -| 29 | (LSB) | -----|-----------------------------------------------------------------------| 30 | | to | (00) | 511 | | ============================================================================== - DMASUP=1 (DMA Supported): The controller supports DMA, and the DMA version of the Send DMA CP command. Instead of writing the CP into the Data Register using PIO, the location of the CP will ge given to the controller. The CP will then be DMA'ed into controller memory. - SGSIZE: The maximum number of entries in the Scatter/Gather table, each entry being 8 bytes long (see 10.5). All other fields are unchanged from PIO EATA.  P- Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 20 10.4 Set DMA Config Set DMA Config is issued to modify the default configuration of the controller. All fields are identical to the PIO EATA. 10.5 Send DMA CP Send DMA CP is used to pass a SCSI CDB, Nexus, or a Vendor Unique command to the controller. The location of the CP is passed to the controller through registers 1F3-1F6. The CP will normally be DMA'ed into the controller using Master Mode DMA. The CP will contain the location of a data buffer. The buffer may be the actual sector location, or a table of locations to be used in Scatter-Gather. After the command is complete, the controller will DMA the SP to the specified location, and optionally DMA Request Sense information in case of an error. All data locations are made available to the driver after the command completes. Table 10-4 describes the data passed in the CP:   Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 21 TABLE 10-4: SEND DMA CP ============================================================================== Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Byte | | | | | | | | | ============================================================================== 0 | DIN | DOUT | (00) | SG | REQSEN | INIT | SRESET | -----|-----------------------------------------------------------------------| 1 | REQUEST SENSE LENGTH | -----|-----------------------------------------------------------------------| 2 | (00) | -----|-----------------------------------------------------------------------| 3 | (00) | -----|-----------------------------------------------------------------------| 4 | (MSB) | - - -|- - DEVICE ADDRESS - -| 7 | (LSB) | -----|-----------------------------------------------------------------------| 8 | MESSAGE 0 | -----|-----------------------------------------------------------------------| 9 | MESSAGE 1 | -----|-----------------------------------------------------------------------| 10 | MESSAGE 2 | -----|-----------------------------------------------------------------------| 11 | MESSAGE 3 | -----|-----------------------------------------------------------------------| 12 | (MSB) | - - -|- - CDB0-11 - -| 23 | (LSB) | -----|-----------------------------------------------------------------------| 24 | (MSB) | - - -|- - DATA TRANSFER LENGTH - -| 27 | (LSB) | -----|-----------------------------------------------------------------------| 28 | (MSB) | - - -|- - VIRTUAL ADDRESS OF CP - -| 31 | (LSB) | -----|-----------------------------------------------------------------------| 32 | (MSB) | - - -|- - DATA ADDRESS - -| 35 | (LSB) | -----|-----------------------------------------------------------------------| 36 | (MSB) | - - -|- - SP ADDRESS - -| 39 | (LSB) | -----|-----------------------------------------------------------------------| 40 | (MSB) | - - -|- - REQUEST SENSE ADDRESS - -| 43 | (LSB) | ============================================================================== - SG=1 indicates that the Data Address is used for Scatter/Gather and contains pointers to the real data locations to read/write data. This bit should only be set if the DMA CP command is issued. - REQSEN=1 indicates that the controller should automatically transfer Target Request Sense Data to the Request Sense Address using DMA. If this bit is cleared, the host may request sense data manually, which is desirable if the Target supports more than the usual number of sense bytes. This bit  . Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 22 should only be set if the DMA CP command is issued. - REQUEST SENSE LENGTH: The number of bytes requested by the controller in response to a Check Status. This field shall only be valid if REQSEN=1. - DATA TRANSFER LENGTH: If SG=0, this field contains the maximum number of bytes transferred by the target to or from host memory. If SG=1, this field contains the total Scatter/Gather packet length in bytes. - DATA ADDRESS: The location of data to be read or written if SG=0, or the location of a buffer containing data locations to be used in a Scatter/ Gather operation if SG=1. The format is as follows: Byte x Byte x..x+3 Byte x+4..x+7 -------- -------------------- ------------------- Byte 0 Location 0 Pointer Location 0 Length Byte 8 Location 1 Pointer Location 1 Length Byte 12 Location 2 Pointer Location 2 Length Byte 16 Location 3 Pointer Location 3 Length ... Byte n Location n Pointer Location n Length - SP ADDRESS: The location to DMA the SP to after the CP has completed. The host should, upon interrupt, examine all SP locations for an EOC bit set. Therefore, before the Send DMA CP command is issued, the host shall assure that EOC is cleared. - REQUEST SENSE ADDRESS: The location to DMA the Request Sense Data to if the CP command ends in error. All other fields are unchanged from PIO EATA. 10.6 EATA Master Mode DMA Command Protocol The method of passing the CP and Data is much simpler with DMA than PIO, however, it does not conform to ATA handshaking. The following is a typical example of a request for data transfer by the drive to the controller. (a) The OS determines a need for a data transfer to or from the controller. (b) The OS instructs a driver to create a CP containing the CDB and data location. Buffer locations shall be reserved for the CP, SP, Data, and optionally Request Sense Data. (c) The driver checks the state of Busy in the Status Register. If Busy is set, the controller is still in the process of accepting the last CP. The driver should not queue the command but wait until Busy is negated. If the driver has exceeded the queue size reported by the Read Config command, Busy shall not be negated until a command is completed by the controller. (d) The driver writes the CP location to the controller and then writes the Send DMA CP opcode to the Command Register. The driver may return to the OS and wait for command completion. (e) The controller begins processing of the new command. (f) The controller will use the data location in the CP to either DMA actual sector data, or to use as a table of pointers for a Scatter-Gather operation, depending on the state of the SG bit in the CP. (g) At some later time, the controller will interrupt the driver to signal command completion, but not necessarily for the command last issued. The driver shall check the EOC bit in each SP to determine which command has completed. Once an EOC is found, the logical thread is re-established and the driver may post command completion to the OS. Error information is located in the SP and optionally the Request Sense Data buffer. . Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 23 11. Timing 11.1 Deskewing The host shall provide cable deskewing for all signals originating from the controller. The controller shall provide for cable deskewing for all signals originating at the host. 11.2 Symbols Certain symbols are used in the timing diagrams. These symbols and their respective definitions are listed below. / or \ - signal transition (asserted or negated) * < or > - data transition (asserted or negated) XXXXXX - undefined but not necessarily released . . . - the "other" condition if a signal is shown with no change #n - used to number the sequence in which events occur e.g. #a, #b _ _ __ __/_ _/ - a degree of uncertainty as to when a signal may be asserted __ _ _ \_ _\__ - a degree of uncertainty as to when a signal may be negated * All signals are shown with the Asserted condition facing to the top of the page. The Negated condition is shown towards the bottom of the page relative to the Asserted condition. 11.3 Terms The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics. In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted e.g. the following illustrates the representation of a signal named TEST going from negated to asserted and back to negated, based on the polarity of the signal. Assert Negate | | Bit Setting=1 |__________| Bit Setting=0 TEST _____/ \_______ Assert Negate | | Bit Setting=0 |__________| Bit Setting=1 TEST- _____/ \_______  h) Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 24 11.6 Command Protocol Timing In Figure 11-4 and Figure 11-5 a state change is indicated by Allow Overlapped Cmds (usually before and after each sequence). If BSY=0 at these points, the controller shall allow a new command to be issued if the option is supported, as indicated by OCSENA=1 in the Read Config command. - The occurrence of an interrupt indicates the beginning of a context switch for the operating system. The interrupt is finally negated when the operating system services the interrupt. Note that some systems may not read the Status Register. The interrupt can be cleared: - after the PIO transfer completes, or - after the driver reads the Status Register, or - if another Command Block Register write starts another command cycle. - Reading of the status register, 1F7, shall clear INTRQ, the interrupt to the PC AT enabled by INTDS=1 in the Fixed Disk Register. - BSY=1 shall automatically be set when the command register is loaded, and BSY=0 shall be set when INTRQ is asserted. If a data transfer is to occur, DRQ=1 when BSY=0. INTRQ may or may not be asserted. - The timing diagrams assume a Pad Length of 0. - A new interrupt shall not be asserted until the previous one has been cleared (to prevent nested interrupts). - If MORE is set interrupts shall not be asserted at the end of each block on PIO EATA transfers. Allow Overlap Cmds Allow Overlap Cmds | Send CP Cmd Truncate Xfr Cmd | | | | | | | | | _ _ _ _ __________ _______________ _ _ _ _ _ _ BSY _ _ _ _ _\_________/ \__________/ \ _ _ _ _ _ __________ DRQ ______________________________/ \____________________________ INTRQ______________________________________________________________________ DATA ___________________________________|||||||____________________________ MORE ______________________________________________________________________ | | | | Request CP Data | CP Data FIGURE 11-4: SEND CP PROTOCOL  ' Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 25 Allow Overlap Cmds End of Cmd | Receive SP Cmd Truncate Xfr Cmd or More Data | | | | | | | | _ _ _ _ __________ _______________ BSY _ _ _ _ _\_________/ \__________/ \____________ __________ _ _ _ _ _ _ DRQ ______________________________/ \_______________/_ _ _ _ _ _ ______ _ _ _ _ _ _ INTRQ_________/ \________________________________________/_ _ _ _ _ _ DATA ___________________________________|||||||____________________________ _ _ _ _ _ _ MORE _________________________________________________________/_ _ _ _ _ _ | | | | | | | Request SP Data | | | Interrupt to Driver SP Data FIGURE 11-5: RECEIVE SP PROTOCOL  P Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 26 Annex A: Protocol Overview for a Driver (informative). The following explanation of the protocol can be used as an outline for a driver conforming to the EATA specification using PIO. 1) The operating system first determines that it has to issue a command to a disk drive. A driver is called which builds the CP, consisting of a CDB and Nexus. 2) The driver has to next determine if a command is currently being executed by the controller. If so, the driver has to determine if Overlapped Command support is enabled. If not, the command has to be queued in an operating system dependent method and may be issued to the controller when the current command completes. 3) If no command is active on the controller, or overlapped commands are supported, the driver has to check for BSY=0 in the Status register. If BSY=1, the driver may choose to wait for BSY=0, or may return to the calling routine and check BSY later. 4) When BSY=0, the driver has to issue the Send CP command, causing BSY=1 to be set. The driver has to wait until DRQ=1, indicating that the HBA requests a data transfer. When DRQ=1, the driver has to write the CP and CP Pad into the data register using PIO. After these bytes are transferred, the driver issues the Truncate Transfer command, causing BSY=1 to be set. 5) With a command now being processed by the controller, the driver may wait for a controller interrupt, or context switch back to the calling routine. If command overlap is not enabled, the driver may chose to poll for BSY=0, an indication that a controller interrupt has occurred. 6) When a controller interrupt occurs, the driver has to determine if a Receive SP should be issued. The Receive SP command has to be issued if commands are overlapped to determine the Nexus corresponding to a previously issued command. If Receive SP is issued and EOC=1, the driver considers the command complete and returns status to the calling routine. If other commands are queued by the operating system, they may be issued at this time. 7) If Receive SP was not issued, or if EOC=0, the driver has to enter a loop testing MORE and DRQ. MORE indicates to the driver that a data transfer may occur very soon. The controller may arbitrarily choose to negate MORE and not actually transfer data. This may be the case when the controller assumed that data was available, but then determined otherwise. If MORE=0, the driver should leave the loop and check for command completion. If DRQ=1, the driver transfers a 512 byte block through the data register using PIO. The driver has to then re-enter the loop testing MORE and DRQ. 8) At any time during the testing of MORE and DRQ, the driver may choose to context switch back to the operating system and handle possible real-time events. The controller always interrupts when DRQ=1 so that the operating system can be made aware of the pending data transfer. 9) When MORE=0, the driver checks for command completion. If overlapped commands are not enabled, BSY may be checked. If BSY=0, the command is considered complete. If BSY=1, the driver waits for another interrupt, as there is possibly more data to be transferred later. 10) If overlapped commands are enabled, the driver has to issue the Receive SP command to detect a possible end of command condition, as indicated by EOC=1. If EOC=0, the driver has to wait for another interrupt. 11) If a command is determined to be complete, the driver reports command status to the operating system. This status may be found in the SP or  . Common Access Method EATA Protocol Rev 1.7a January 26, 1990 Page 27 the standard ATA Error and Status register. If an error is detected, a Request Sense command may be issued via the Send CP command for more detailed information.