Document revision date: 19 July 1999

This section describes VAX vector architecture integer instructions.

Vector Integer Add

Format

vector + vector:

VVADDL [/0|1] Va, Vb, Vc

scalar + vector:

VSADDL [/0|1] scalar, Vb, Vc

Format

vector + vector: opcode cntrl.rw

scalar + vector: opcode cntrl.rw, addend.rl

Opcodes

80FD	VVADDL	Vector Vector Add Longword
81FD	VSADDL	Vector Scalar Add Longword

vector_control_word

Exceptions

• integer overflow

Description

The scalar addend or Va operand is added, elementwise, to vector register Vb and the 32-bit sum is written to vector register Vc. Only bits <31:0> of each vector element participate in the operation. Bits <63:32> of the elements of vector register Vc are UNPREDICTABLE. The length of the vector is specified by the Vector Length Register (VLR).

If integer overflow is detected and cntrl<EXC> is set, the exception type and destination register number are recorded in the Vector Arithmetic Exception Register (VAER) and the vector operation is allowed to complete. On integer overflow, the low-order 32 bits of the true result are stored in the destination element.

Vector Integer Compare

Format

vector--vector:

{VVGTRL | VVEQLL |VVLSSL |VVLEQL|VVNEQL|VVGEQL} [/0|1] Va, Vb

scalar--vector:

{VSGTRL|VSEQLL|VSLSSL|VSLEQL|VSNEQL|VSGEQL} [/0|1] src, Vb

Format

vector--vector: opcode cntrl.rw

scalar--vector: opcode cntrl.rw, src.rl

Opcodes

C0FD	VVCMPL	Vector Vector Compare Longword
C1FD	VSCMPL	Vector Scalar Compare Longword

vector_control_word

The condition being tested is determined by cntrl<2:0>, as follows:

Value of cntrl<2:0>	Meaning
0	Greater than
1	Equal
2	Less than
3	Reserved 1
4	Less than or equal
5	Not equal
6	Greater than or equal
7	Reserved 1

Description

The scalar or Va operand is compared, elementwise, with vector register Vb. The length of the vector is specified by the Vector Length Register (VLR). For each element comparison, if the specified relationship is true, the Vector Mask Register bit (VMR<i>) corresponding to the vector element is set to one; otherwise, it is cleared. If cntrl<MOE> is set, VMR bits corresponding to elements that do not match cntrl<MTF> are left unchanged. VMR bits beyond the vector length are left unchanged. Only bits <31:0> of each vector element participate in the operation.

Vector Integer Multiply

Format

vector * vector:

VVMULL [/V[0|1]] Va, Vb, Vc

scalar * vector:

VSMULL [/V[0|1]] scalar, Vb, Vc

Format

vector * vector: opcode cntrl.rw

scalar * vector: opcode cntrl.rw, mulr.rl

Opcodes

A0FD	VVMULL	Vector Vector Multiply Longword
A1FD	VSMULL	Vector Scalar Multiply Longword

vector_control_word

Exceptions

• integer overflow

Description

The scalar multiplier or vector operand Va is multiplied, elementwise, by vector operand Vb and the least significant 32 bits of the signed 64-bit product are written to vector register Vc. Only bits <31:0> of each vector element participate in the operation. Bits <63:32> of the elements of vector register Vc are UNPREDICTABLE. The length of the vector is specified by the Vector Length Register (VLR).

If integer overflow is detected and cntrl<EXC> is set, the exception condition type and destination register number are recorded in the Vector Arithmetic Exception Register (VAER) and the vector operation is allowed to complete. On integer overflow, the low-order 32 bits of the true result are stored in the destination element.

Vector Integer Subtract

Format

vector--vector:

VVSUBL [/V[0|1]] Va, Vb, Vc

scalar--vector:

VSSUBL [/V[0|1]] scalar, Vb, Vc

Format

vector--vector: opcode cntrl.rw

scalar--vector: opcode cntrl.rw, min.rl

Opcodes

88FD	VVSUBL	Vector Vector Subtract Longword
89FD	VSSUBL	Vector Scalar Subtract Longword

vector_control_word

Exceptions

• integer overflow

Description

The vector operand Vb is subtracted, elementwise, from the scalar minuend or vector operand Va. The 32-bit difference is written to vector register Vc. Only bits <31:0> of each vector element participate in the operation. Bits <63:32> of the elements of vector register Vc are UNPREDICTABLE. The length of the vector is specified by the Vector Length Register (VLR).

If integer overflow is detected and cntrl<EXC> is set, the exception condition type and destination register number are recorded in the Vector Arithmetic Exception Register (VAER) and the vector operation is allowed to complete. On integer overflow, the low-order 32 bits of the true result are stored in the destination element.

This section describes VAX vector architecture logical and shift instructions.

Vector Logical Functions

Format

vector op vector:

• VVBISL
• VVXORL
• VVBICL

[/V[0|1]] Va, Vb, Vc

vector op scalar:

• VSBISL
• VSXORL
• VSBICL

[/V[0|1]] scalar, Vb, Vc

Format

op vector: opcode cntrl.rw

op scalar: opcode cntrl.rw, src.rl

Opcodes

C8FD	VVBISL	Vector Vector Bit Set Longword
E8FD	VVXORL	Vector Vector Exclusive-OR Longword
CCFD	VVBICL	Vector Vector Bit Clear Longword
C9FD	VSBISL	Vector Scalar Bit Set Longword
E9FD	VSXORL	Vector Scalar Exclusive-OR Longword
CDFD	VSBICL	Vector Scalar Bit Clear Longword

vector_control_word

Exceptions

• None.

Description

The scalar src or vector operand Va is combined, elementwise, using the specified Boolean function, with vector register Vb and the result is written to vector register Vc. Only bits <31:0> of each vector element participate in the operation. Bits <63:32> of the elements of Vb are written into bits <63:32> of the corresponding elements of Vc. The length of the vector is specified by the Vector Length Register (VLR).

Vector Shift Logical

Format

vector shift count:

• VVSRLL
• VVSLLL

[/V[0|1]] Va, Vb, Vc

scalar shift count:

• VSSRLL
• VSSLLL

[/V[0|1]] cnt, Vb, Vc

Format

vector shift count: opcode cntrl.rw

scalar shift count: opcode cntrl.rw, cnt.rl

Opcodes

E0FD	VVSRLL	Vector Vector Shift Right Logical Longword
E4FD	VVSLLL	Vector Vector Shift Left Logical Longword
E1FD	VSSRLL	Vector Scalar Shift Right Logical Longword
E5FD	VSSLLL	Vector Scalar Shift Left Logical Longword

vector_control_word

Exceptions

• None.

Description

Each element in vector register Vb is shifted logically left or right 0 to 31 bits as specified by a scalar count operand or vector register Va. The shifted results are written to vector register Vc. Zero bits are propagated into the vacated bit positions. Only bits <4:0> of the count operand and bits <31:0> of each Vb element participate in the operation. Bits <63:32> of the elements of vector register Vc are UNPREDICTABLE. The length of the vector is specified by the Vector Length Register (VLR).

The VAX vector architecture provides instructions for operating on F_floating, D_floating, and G_floating operand formats. The floating-point arithmetic instructions are add, subtract, compare, multiply, and divide. Data conversion instructions are provided to convert operands between D_floating, G_floating, F_floating, and longword integer.

Rounding is performed using standard VAX rounding rules. The accuracy of the vector floating-point instructions matches that of the scalar floating-point instructions. Refer to the section on floating-point instructions in the VAX Architecture Reference Manual for more information.

1.13.1 Vector Floating-Point Exception Conditions

All vector floating-point exception conditions occur asynchronously with respect to the scalar processor. These exception conditions do not interrupt the scalar processor. If the exception condition is enabled, then the exception condition type and destination register number are recorded in the Vector Arithmetic Exception Register (VAER), and a reserved operand in the format of the instruction's data type is written into the destination register element. Encoded in this reserved operand is the exception condition type. After recording the exception and writing the appropriate result into the destination register element, the instruction encountering the exception continues executing to completion.

If a vector convert floating to integer instruction encounters a source element that is a reserved operand, an UNPREDICTABLE result rather than a reserved operand is written into the destination register element.

Figure 1-13 shows the encoding of the reserved operand that is written for vector floating-point exceptions. Consistent with the definition of a reserved operand, the sign bit (bit <15>) is one and the exponent (bits <14:7> for F_floating and D_floating, and bits <14:4> for G_floating) is zero. When the reserved operand is written in F_floating or D_floating format, bits <6:4> are also zero. The exception condition type (ETYPE) is encoded in bits <3:0>, as shown in Table 1-16. If a reserved operand is divided by zero, both ETYPE bits may be set. The state of all other bits in the result (denoted by shading) is UNPREDICTABLE.

If the floating underflow exception condition is suppressed by cntrl<EXC>, a zero result is written to the destination register element and no further action is taken. Floating overflow, floating divide by zero, and floating reserved operand are always enabled.

Figure 1-13 Encoding of the Reserved Operand

Table 1-16 Encoding of the Exception Condition Type (ETYPE)

Bit	Exception Condition Type
<0>	Floating underflow
<1>	Floating divide by zero
<2>	Floating reserved operand
<3>	Floating overflow

1.13.2 Floating-Point Instructions

This section describes VAX vector architecture floating-point instructions.

Vector Floating Add

Format

vector + vector:

• VVADDF
• VVADDD
• VVADDG

[/U[0|1]] Va, Vb, Vc

scalar + vector:

• VSADDF
• VSADDD
• VSADDG

[/U[0|1]] scalar, Vb, Vc

Format

vector + vector:

opcode cntrl.rw

scalar + vector (F_floating):

opcode cntrl.rw, addend.rl

scalar + vector (D_ and G_floating):

opcode cntrl.rw, addend.rq

Opcodes

84FD	VVADDF	Vector Vector Add F_Floating
85FD	VSADDF	Vector Scalar Add F_Floating
86FD	VVADDD	Vector Vector Add D_Floating
87FD	VSADDD	Vector Scalar Add D_Floating
82FD	VVADDG	Vector Vector Add G_Floating
83FD	VSADDG	Vector Scalar Add G_Floating

vector_control_word

Exceptions

• floating overflow
• floating reserved operand
• floating underflow

Description

The source addend or vector operand Va is added, elementwise, to vector register Vb and the sum is written to vector register Vc. The length of the vector is specified by the Vector Length Register (VLR).

In VxADDF, only bits <31:0> of each vector element participate in the operation. Bits <63:32> of the destination vector elements are UNPREDICTABLE.

If a floating underflow occurs when cntrl<EXC> is set or if a floating overflow or floating reserved operand occurs, an encoded reserved operand is stored as the result and the exception condition type and destination register number are recorded in the Vector Arithmetic Exception Register (VAER). The vector operation is then allowed to complete. If cntrl<EXC> is clear, zero is written to the destination element when an exponent underflow occurs and no other action is taken.

Vector Floating Compare

Format

vector--vector:

• VVGTRF
• VVGTRD
• VVGTRG
• VVEQLF
• VVEQLD
• VVEQLG
• VVLSSF
• VVLSSD
• VVLSSG
• VVLEQF
• VVLEQD
• VVLEQG
• VVNEQF
• VVNEQD
• VVNEQG
• VVGEQF
• VVGEQD
• VVGEQG

[/U[0|1]] Va, Vb

scalar--vector:

• VSGTRF
• VSGTRD
• VSGTRG
• VSEQLF
• VSEQLD
• VSEQLG
• VSLSSF
• VSLSSD
• VSLSSG
• VSLEQF
• VSLEQD
• VSLEQG
• VSNEQF
• VSNEQD
• VSNEQG
• VSGEQF
• VSGEQD
• VSGEQG

[/U[0|1]] src, Vb

Architecture

Format

vector--vector:

opcode cntrl.rw

scalar--vector (F_floating):

opcode cntrl.rw, src.rl

scalar--vector (D_ and G_floating):

opcode cntrl.rw, src.rq

Opcodes

C4FD	VVCMPF	Vector Vector Compare F_floating
C5FD	VSCMPF	Vector Scalar Compare F_floating
C6FD	VVCMPD	Vector Vector Compare D_floating
C7FD	VSCMPD	Vector Scalar Compare D_floating
C2FD	VVCMPG	Vector Vector Compare G_floating
C3FD	VSCMPG	Vector Scalar Compare G_floating

vector_control_word

The condition being tested is determined by cntrl<2:0>, as follows:

Value of cntrl<2:0>	Meaning
0	Greater than
1	Equal
2	Less than
3	Reserved 1
4	Less than or equal
5	Not equal
6	Greater than or equal
7	Reserved 1

Exceptions

• floating reserved operand

Description

The scalar or vector operand Va is compared, elementwise, with vector register Vb. The length of the vector is specified by the Vector Length Register (VLR). For each element comparison, if the specified relationship is true, the Vector Mask Register bit (VMR<i>) corresponding to the vector element is set to one, otherwise it is cleared. If cntrl<MOE> is set, VMR bits corresponding to elements that do not match cntrl<MTF> are left unchanged. VMR bits beyond the vector length are left unchanged. If an element being compared is a reserved operand, VMR<i> is UNPREDICTABLE. In VxCMPF, only bits <31:0> of each vector element participate in the operation.

If a floating reserved operand exception occurs, the exception condition type is recorded in the Vector Arithmetic Exception Register (VAER) and the vector operation is allowed to complete.

Note that for this instruction, no bits are set in the VAER destination register mask when an exception occurs.

Vector Convert

Format

• VVCVTLF
• VVCVTLD
• VVCVTLG
• VVCVTFL
• VVCVTRFL
• VVCVTFD
• VVCVTFG
• VVCVTDL
• VVCVTDF
• VVCVTRDL
• VVCVTGL
• VVCVTGF
• VVCVTRGL

[/U[0|1]] Vb, Vc

Format

opcode cntrl.rw

Opcodes

ECFD

VVCVT

Vector Convert

vector_control_word

Cntrl<11:8> specifies the conversion to be performed, as follows:

cntrl<11:8>	Meaning
1 1 1 1	CVTRGL (Convert Rounded G_Floating to Longword)
1 1 1 0	Reserved 1
1 1 0 1	CVTGF (Convert Rounded G_Floating to F_Floating)
1 1 0 0	CVTGL (Convert Truncated G_Floating to Longword)
1 0 1 1	Reserved 1
1 0 1 0	CVTRD (Convert Rounded D_Floating to Longword)
1 0 0 1	CVTDF (Convert Rounded D_Floating to F_Floating)
1 0 0 0	CVTDL (Convert Truncated D_Floating to Longword)
0 1 1 1	CVTFG (Convert F_Floating to G_Floating (exact))
0 1 1 0	CVTFD (Convert F_Floating to D_Floating (exact))
0 1 0 1	CVTRF (Convert Rounded F_Floating to Longword)
0 1 0 0	CVTFL (Convert Truncated F_Floating to Longword)
0 0 1 1	CVTLG (Convert Longword to G_Floating (exact))
0 0 1 0	CVTLD (Convert Longword to D_Floating (exact))
0 0 0 1	CVTLF (Convert Rounded Longword to F_Floating)
0 0 0 0	Reserved 1

Exceptions

• floating overflow
• floating reserved operand
• floating underflow
• integer overflow

Description

The vector elements in vector register Vb are converted and results are written to vector register Vc. Cntrl<11:8> specifies the conversion to be performed. The length of the vector is specified by the Vector Length Register (VLR). Bits <63:32> of Vc are UNPREDICTABLE for instructions that convert from D_floating or G_floating to F_floating or longword. When CVTRGL, CVTRDL, and CVTRFL round, the rounding is done in sign magnitude, before conversion to two's complement.

If an integer overflow occurs when cntrl<EXC> is set, the low-order 32 bits of the true result are written to the destination element as the result, and the exception condition type and destination register number are recorded in the Vector Arithmetic Exception Register (VAER). The vector operation is then allowed to complete. If integer overflow occurs when cntrl<EXC> is clear, the low-order 32 bits of the true result are written to the destination element, and no other action is taken.

For vector convert floating to integer, where the source element is a reserved operand, the value written to the destination element is UNPREDICTABLE. In addition, the exception type and destination register number are recorded in the VAER. The vector operation is then allowed to complete.

For vector convert floating to floating instructions, if floating underflow occurs when cntrl<EXC> is clear, zero is written to the destination element, and no other action is taken. The vector operation is then allowed to complete.

For vector convert floating to floating instructions, if floating underflow occurs with cntrl<EXC> set or if a floating overflow or reserved operand occurs, an encoded reserved operand is written to the destination element, and the exception condition type and destination register number are recorded in the VAER. The vector operation is then allowed to complete.

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