Document revision date: 19 July 1999

Contents

Chapter 1
1	VAX Vector Architecture
1.1	Introduction to VAX Vector Architecture
1.2	VAX Vector Architecture Registers
1.2.1	Vector Registers
1.2.2	Vector Control Registers
1.2.3	Internal Processor Registers
1.3	Vector Instruction Formats
1.3.1	Masked Operations
1.3.2	Exception Enable Bit
1.3.3	Modify Intent Bit
1.3.4	Register Specifier Fields
1.3.5	Vector Control Word Formats
1.3.6	Restrictions on Operand Specifier Usage
1.3.7	VAX Condition Codes
1.3.8	Illegal Vector Opcodes
1.4	Assembler Notation
1.5	Execution Model
1.5.1	Access Mode Restrictions
1.5.2	Scalar Context Switching
1.5.3	Overlapped Instruction Execution
1.5.3.1	Vector Chaining
1.5.3.2	Register Conflict
1.5.3.3	Dependencies Among Vector Results
1.6	Vector Processor Exceptions
1.6.1	Vector Memory Management Exception Handling
1.6.2	Vector Arithmetic Exceptions
1.6.3	Vector Processor Disabled
1.6.4	Handling Disabled Faults and Vector Context Switching
1.6.5	MFVP Exception Reporting Examples
1.7	Synchronization
1.7.1	Scalar/Vector Instruction Synchronization (SYNC)
1.7.2	Scalar/Vector Memory Synchronization
1.7.2.1	Memory Instruction Synchronization (MSYNC)
1.7.2.2	Memory Activity Completion Synchronization (VMAC)
1.7.3	Other Synchronization Between the Scalar and Vector Processors
1.7.4	Memory Synchronization Within the Vector Processor (VSYNC)
1.7.5	Required Use of Memory Synchronization Instructions
1.7.5.1	When VSYNC Is Not Required
1.8	Memory Management
1.9	Hardware Errors
1.10	Vector Memory Access Instructions
1.10.1	Alignment Considerations
1.10.2	Stride Considerations
1.10.3	Context of Address Specifiers
1.10.4	Access Mode
1.10.5	Memory Instructions
Command 1	VLD
Command 2	VGATH
Command 3	VST
Command 4	VSCAT
1.11	Vector Integer Instructions
Command 5	VADDL
Command 6	VCMPL
Command 7	VMULL
Command 8	VSUBL
1.12	Vector Logical and Shift Instructions
Command 9	VBIC, VBIS, and VXOR
Command 10	VSL
1.13	Vector Floating-Point Instructions
1.13.1	Vector Floating-Point Exception Conditions
1.13.2	Floating-Point Instructions
Command 11	VADD
Command 12	VCMP
Command 13	VVCVT
Command 14	VDIV
Command 15	VMUL
Command 16	VSUB
1.14	Vector Edit Instructions
Command 17	VMERGE
Command 18	IOTA
1.15	Miscellaneous Instructions
Command 19	MFVP
Command 20	MTVP
Command 21	VSYNC
Index
Index
Figures
1-1	Vector Register
1-2	Vector Length Register (VLR)
1-3	Vector Mask Register (VMR)
1-4	Vector Count Register (VCR)
1-5	Vector Processor Status Register (VPSR)
1-6	Vector Arithmetic Exception Register (VAER)
1-7	Vector Memory Activity Check (VMAC) Register
1-8	Vector Translation Buffer Invalidate All (VTBIA) Register
1-9	Vector State Address Register (VSAR)
1-10	Vector Control Word Operand (cntrl)
1-11	Vector Control Word Format
1-12	Memory Management Fault Stack Frame (as Sent by the Vector Processor)
1-13	Encoding of the Reserved Operand
Tables
1-1	Description of the Vector Processor Status Register (VPSR)
1-2	Possible VPSR <3:0 > Settings for MTPR
1-3	State of the Vector Processor
1-4	VAER Exception Condition Summary Word Encoding
1-5	IPR Assignments
1-6	Description of the Vector Control Word Operand
1-7	Dependencies for Vector Operate Instructions
1-8	Dependencies for Vector Load and Gather Instructions
1-9	Dependencies for Vector Store and Scatter Instructions
1-10	Dependencies for Vector Compare Instructions
1-11	Dependencies for Vector MERGE Instructions
1-12	Dependencies for IOTA Instruction
1-13	Dependencies for MFVP Instructions
1-14	Miscellaneous Dependencies
1-15	Possible Pairs of Read and Write Operations When Scalar/Vector Memory Synchronization (M) or VSYNC (V) Is Required Between Instructions That Reference the Same Memory Location
1-16	Encoding of the Exception Condition Type (ETYPE)

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