Document revision date: 19 July 1999

A
Access mode
vector #1
vector #2
vector #3
Address
translation vector
Addressing mode
immediate
usage restricted in vector memory instructions
usage restricted in vector memory instructions
Alignment vector #1
Alignment vector #2
Assembler notation
Asynchronous memory management exception handling #1
Asynchronous memory management exception handling #2
C
Chaining of vector instructions
Context switch
scalar #1
scalar #2
scalar #3
vector
D
Default result
vector arithmetic exceptions #1
vector arithmetic exceptions #2
vector arithmetic exceptions #3
Dependencies
vector results
Disabled fault
vector processor #1
vector processor #2
E
Edit
instruction
vector
ETYPE #1
ETYPE #2
Exception
vector processor #1
vector processor #2
vector processor #3
arithmetic #1
arithmetic #2
arithmetic #3
arithmetic #4
arithmetic #5
floating-point
memory management
Exception Condition Type
See ETYPE
Execution model
vector processor
F
Floating-point instructions
vector
H
HALT (Halt) instruction
synchronizing vector memory before
Hardware errors
vector #1
vector #2
I
I/O space references
vector #1
vector #2
vector #3
vector #4
Immediate mode addressing
usage restricted in vector memory instructions #1
usage restricted in vector memory instructions #2
Instruction
vector #1
vector #2
vector #3
Integer instructions
vector
Interlocked instructions
Internal processor register
See IPR
Interrupts
IOTA (Generate Compressed Iota Vector) instruction
IPR (internal processor register)
vector #1
vector #2
L
LDPCTX (Load Process Context) instruction #1
LDPCTX (Load Process Context) instruction #2
Logical functions, vector
M
Machine checks #1
Machine checks #2
Masked vector operations #1
Masked vector operations #2
Memory
See Vector memory
Memory management
vector
memory management disabled
TB #1
TB #2
TB #3
TB #4
TB #5
TB #6
TB #7
Memory management exceptions
vector
asynchronous MME handling
fault parameter
PTE bit
VAL bit
VAS bit
VIO bit
fault stack frame
synchronous MME handling
system control block (SCB)
Memory synchronization
required use of
MFPR (Move from Processor Register) instruction
vector IPRs #1
vector IPRs #2
vector IPRs #3
VPSR #1
VPSR #2
VPSR #3
MFVP (Move from Vector Processor) instruction #1
MFVP (Move from Vector Processor) instruction #2
Modify-fault
vector
MSYNC (Memory Instruction Synchronization) instruction #1
MSYNC (Memory Instruction Synchronization) instruction #2
MSYNC (Memory Instruction Synchronization) instruction #3
MSYNC (Memory Instruction Synchronization) instruction #4
MSYNC (Memory Instruction Synchronization) instruction #5
MTPR (Move to Processor Register) instruction
vector IPRs #1
vector IPRs #2
MTVP (Move to Vector Processor) instruction
O
Opcode
illegal vector
Operand specifier
restrictions on usage for vector instructions
Overlapped vector instruction execution
P
Power failure
R
Register
vector
control registers
internal processor registers
Register conflict
vector
S
Scalar/vector memory synchronization
Shift instruction
vector
Short literal mode
usage restricted in vector floating-point instructions
Stride
vector
SYNC (Scalar/Vector Instruction Synchronization) instruction #1
SYNC (Scalar/Vector Instruction Synchronization) instruction #2
SYNC (Scalar/Vector Instruction Synchronization) instruction #3
Synchronization
Synchronous memory management exception handling
System Control Block (SCB) vector
T
TB (Translation buffer)
vector #1
vector #2
vector #3
vector #4
vector #5
vector #6
vector #7
TBIA (TB Invalidate All) instruction
TBIS (TB Invalidate Single) instruction
Translation buffer
See TB
V
VADD (Vector Floating Add) instruction
VADDL (Vector Integer Add) instruction
VAER (Vector Arithmetic Exception Register)
VAX condition codes
VBIC (Vector Bit Clear) instruction
VBIS (Vector Bit Set) instruction
VCMP (Vector Floating Compare) instruction
VCMPL (Vector Integer Compare) instruction
VCR (Vector Count Register) #1
VCR (Vector Count Register) #2
VCR (Vector Count Register) #3
VDIV (Vector Floating Divide) instruction
Vector address translation
Vector control word #1
Vector control word #2
Vector control word #3
EXC (Exception Enable) bit #1
EXC (Exception Enable) bit #2
EXC (Exception Enable) bit #3
EXC (Exception Enable) bit #4
EXC (Exception Enable) bit #5
EXC (Exception Enable) bit #6
EXC (Exception Enable) bit #7
EXC (Exception Enable) bit #8
EXC (Exception Enable) bit #9
EXC (Exception Enable) bit #10
EXC (Exception Enable) bit #11
EXC (Exception Enable) bit #12
EXC (Exception Enable) bit #13
EXC (Exception Enable) bit #14
EXC (Exception Enable) bit #15
EXC (Exception Enable) bit #16
MI (Modify Intent) bit #1
MI (Modify Intent) bit #2
MI (Modify Intent) bit #3
MI (Modify Intent) bit #4
MI (Modify Intent) bit #5
MOE (Masked Operations Enable) bit #1
MOE (Masked Operations Enable) bit #2
MOE (Masked Operations Enable) bit #3
MTF (Match True/False) bit #1
MTF (Match True/False) bit #2
MTF (Match True/False) bit #3
register specifier fields
Vector Count Register
See VCR
Vector instruction
decoding
execution
formats
Vector Length Register
See VLR
Vector Logical Functions
Vector Mask Register
See VMR
Vector memory
access mode #1
access mode #2
accessing page tables
alignment
HALT considerations
indicating intent to modify
instructions
management
See Memory management
required use of synchronization instructions
scalar/vector synchronization of
stride
Vector Memory Activity Check Register
SeeVMAC
Vector processor disabled #1
Vector processor disabled #2
Vector Processor Status Register
See VPSR
Vector registers
Vector State Address Register
See VSAR
VGATH (Gather Memory Data into Vector Register) instruction #1
VGATH (Gather Memory Data into Vector Register) instruction #2
VGATH (Gather Memory Data into Vector Register) instruction #3
VLD (Load Memory Data into Vector Register) instruction #1
VLD (Load Memory Data into Vector Register) instruction #2
VLD (Load Memory Data into Vector Register) instruction #3
VLD (Load Memory Data into Vector Register) instruction #4
VLR (Vector Length Register) #1
VLR (Vector Length Register) #2
VLR (Vector Length Register) #3
VMAC (Vector Memory Activity Check) Register #1
VMAC (Vector Memory Activity Check) Register #2
VMAC (Vector Memory Activity Check) Register #3
VMAC (Vector Memory Activity Check) Register #4
VMAC (Vector Memory Activity Check) Register #5
VMAC (Vector Memory Activity Check) Register #6
VMERGE (Vector Merge) instruction
VMR (Vector Mask Register)
VMR (Vector Mask Register) #1
VMR (Vector Mask Register) #2
VMR (Vector Mask Register) #3
VMUL (Vector Floating Multiply) instruction
VMULL (Vector Integer Multiply) instruction
VPSR (Vector Processor Status Register) #1
VPSR (Vector Processor Status Register) #2
VPSR (Vector Processor Status Register) #3
VPSR (Vector Processor Status Register) #4
VPSR (Vector Processor Status Register) #5
AEX (Arithmetic Exception) bit #1
AEX (Arithmetic Exception) bit #2
AEX (Arithmetic Exception) bit #3
AEX (Arithmetic Exception) bit #4
AEX (Arithmetic Exception) bit #5
AEX (Arithmetic Exception) bit #6
BSY (Busy) bit #1
BSY (Busy) bit #2
BSY (Busy) bit #3
BSY (Busy) bit #4
BSY (Busy) bit #5
BSY (Busy) bit #6
BSY (Busy) bit #7
BSY (Busy) bit #8
BSY (Busy) bit #9
BSY (Busy) bit #10
BSY (Busy) bit #11
IMP (Implementation-Specific Hardware Error) bit
IMP (Implementation-Specific Hardware Error) bit #1
IMP (Implementation-Specific Hardware Error) bit #2
IMP (Implementation-Specific Hardware Error) bit #3
IMP (Implementation-Specific Hardware Error) bit #4
IMP (Implementation-Specific Hardware Error) bit #5
IMP (Implementation-Specific Hardware Error) bit #6
IVO (Illegal Vector Opcode) bit #1
IVO (Illegal Vector Opcode) bit #2
IVO (Illegal Vector Opcode) bit #3
IVO (Illegal Vector Opcode) bit #4
IVO (Illegal Vector Opcode) bit #5
IVO (Illegal Vector Opcode) bit #6
MF (Memory Fault) bit #1
MF (Memory Fault) bit #2
MF (Memory Fault) bit #3
MF (Memory Fault) bit #4
VPSR (Vector Processor Status Register)
PMF (Pending Memory Fault) bit
VPSR (Vector Processor Status Register)
PMF (Pending Memory Fault) bit #1
PMF (Pending Memory Fault) bit #2
PMF (Pending Memory Fault) bit #3
PMF (Pending Memory Fault) bit #4
RLD (State Reload) bit #1
RLD (State Reload) bit #2
RLD (State Reload) bit #3
RST (State Reset) bit #1
RST (State Reset) bit #2
RST (State Reset) bit #3
RST (State Reset) bit #4
RST (State Reset) bit #5
RST (State Reset) bit #6
STS (State Store) bit #1
STS (State Store) bit #2
STS (State Store) bit #3
VEN (Enable) bit #1
VEN (Enable) bit #2
VEN (Enable) bit #3
VEN (Enable) bit #4
VEN (Enable) bit #5
VEN (Enable) bit #6
VEN (Enable) bit #7
VEN (Enable) bit #8
VEN (Enable) bit #9
VEN (Enable) bit #10
VEN (Enable) bit #11
VEN (Enable) bit #12
VEN (Enable) bit #13
VEN (Enable) bit #14
VSAR (Vector State Address Register)
VSCAT (Scatter Vector Register Data into Memory) instruction #1
VSCAT (Scatter Vector Register Data into Memory) instruction #2
VSCAT (Scatter Vector Register Data into Memory) instruction #3
VSCAT (Scatter Vector Register Data into Memory) instruction #4
VSL (Vector Shift Logical) instruction
VST (Store Vector Register Data into Memory) instruction #1
VST (Store Vector Register Data into Memory) instruction #2
VST (Store Vector Register Data into Memory) instruction #3
VST (Store Vector Register Data into Memory) instruction #4
VSUB (Vector Floating Subtract) instruction
VSUBL (Vector Integer Subtract) instruction
VSYNC (Synchronize Vector Memory Access) instruction #1
VSYNC (Synchronize Vector Memory Access) instruction #2
VSYNC (Synchronize Vector Memory Access) instruction #3
VSYNC (Synchronize Vector Memory Access) instruction #4
VTBIA (Vector TB Invalidate All) instruction #1
VTBIA (Vector TB Invalidate All) instruction #2
VTBIA (Vector TB Invalidate All) instruction #3
VTBIA (Vector TB Invalidate All) instruction #4
VTBIA (Vector TB Invalidate All) instruction #5
VTBIA (Vector TB Invalidate All) instruction #6
VVCVT (Vector Convert) instruction
VXOR (Vector Exclusive Or) instruction

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