Interrupt Behaviour of the Z80 CPU

by Achim Flammenkamp

Interrupt timing

• NMI
  It takes 11 clock cycles to get to #0066:
  1. M1 cycle: 5 T states to do an opcode read and decrement SP
  2. M2 cycle: 3 T states write high byte of PC to the stack and decrement SP
  3. M3 cycle: 3 T states write the low byte of PC and jump to #0066.
• INT and interrupt mode 0 set
  In this mode, timing depends on the instruction put on the bus. The interrupt processing last 2 clock cycles more than this instruction usually needs.
  Two typical examples follow:
  
  a RST n on the data bus, it takes 13 cycles to get to 'n':
  1. M1 cycle: 7 ticks
     acknowledge interrupt and decrement SP
  2. M2 cycle: 3 ticks
     write high byte and decrement SP
  3. M3 cycle: 3 ticks
     write low byte and jump to 'n'
  With a CALL nnnn on the data bus, it takes 19 cycles:
  1. M1 cycle: 7 ticks
     acknowledge interrupt
  2. M2 cycle: 3 ticks
     read low byte of 'nnnn' from data bus
  3. M3 cycle: 3 ticks
     read high byte of 'nnnn' and decrement SP
  4. M4 cycle: 3 ticks
     write high byte of PC to the stack and decrement SP
  5. M5 cycle: 3 ticks
     write low byte of PC and jump to 'nnnn'.
• INT and interrupt mode 1 set
  It takes 13 clock cycles to reach #0038:
  1. M1 cycle: 7 ticks
     acknowledge interrupt and decrement SP
  2. M2 cycle: 3 ticks
     write high byte of PC onto the stack and decrement SP
  3. M3 cycle: 3 ticks
     write low byte onto the stack and to set PC to #0038.
• INT and interrupt mode 2 set
  It takes 19 clock cycles to get to the interrupt routine:
  1. M1 cycle: 7 ticks
     acknowledge interrupt and decrement SP
  2. M2 cycle: 3 ticks
     write high byte of PC onto stack and decrement SP
  3. M3 cycle: 3 ticks
     write low byte onto the stack
  4. M4 cycle: 3 ticks
     read low byte from the interrupt vector
  5. M5 cycle: 3 ticks
     read high byte from bus and jump to interrupt routine

1. "acknowledge interrupt" means pin IORQ gets together with M1-pin active/low. Furthermore the CPU adds 2 wait states to the normal machine cycle.
2. Quoted remark:
   • If a LD A,I or LD A,R (which copy IFF2 to the P/V flag) is interrupted, then the P/V flag is reset, even if interrupts were enabled beforehand.
   • If interrupts are disabled when a EI instruction is interrupted, then the interrupt will not occur until after the instruction following the EI, as when IFF1 is sampled during the one and only machine-cycle of the EI, it will be reset.
3. An INT will let the INT-pin low(active) until it is indirectly reseted by an RETI or other external hardware. In contrast a signal at the NMI-pin will be recognized when its state going from high to low! Thus it is not a level trigger signal, but a pulse which is stored internally by the CPU until the next M1 cycle.

Reset Timing

It takes 3 clock cycles:
• IFF1 and IFF2 as well as interrupt mode is set to 0
• PC is set to 0, I and R registers are reset also.
• SP is set to 0xffff as well as the A and the F register is set to 0xff.

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